1. Technical Field
The invention relates to ferroelectric memory devices, and more particularly, to sense amplifier circuits, equalizer circuits and positive potential converter circuits for read-out operations of ferroelectric memory devices.
2. Related Art
A ferroelectric memory device (FeRAM) may generally use a method using a latch type sense amplifier circuit for its read-out operation. For example, Japanese laid-open patent application JP-A-2000-187990 (corresponding to U.S. Pat. No. 6,233,170) (referred to as a “first patent document”) is an example of related art.
However, in this case, a voltage that is applied to a plate line is voltage-divided into a ferroelectric capacitor capacitance (Cs) and a bit line capacitance (Cb1). Accordingly, a sufficient potential would not be applied to the ferroelectric capacitor due to the bit line capacitance (Cb1). Also, a difference in the bit line voltage is amplified by the sense amplifier for read-out. Therefore, the more the bit line capacitance (Cb1) increases, the smaller the bit line voltage becomes, which results in a smaller sensing margin.
In this connection, read-out circuits that are capable of virtually fixing the bit line to the ground potential are being examined. For example, Japanese laid-open patent application JP-A-2002-133857 (corresponding to U.S. Pat. No. 648,703) (referred to as a “second patent document”), and IEEE Journal of Solid-State Circuits, Vol. 37, No. 5, May 2003 “Bit line GND Sensing Technique for Low-Voltage Operation FeRAM” are examples of related art.
(1) However, as described below in greater detail, the use of the circuit described in the aforementioned second patent document entails the following problems: (a) each of the elements composing the circuit requires fine fitting according to the ferroelectric characteristics; (b) the timing at which the sensing margin becomes maximum may change; (c) through-current may flow through the inverter during read-out operation; and (d) the circuit is large in area.
(2) Furthermore, in the circuit described in the aforementioned second patent document, the read-out operation is conducted through transferring the charge read out from the memory cell to a capacitor that is charged to a negative potential. Therefore, negative potential nodes (for example, VMN and VTH in FIG. 3 of the document) are generated. However, these nodes are put in a floating state on standby, such that the initial potential becomes unstable. As the initial potential changes, the output potential at read-out also changes, which results in a reduced sensing margin.
(3) Moreover, in the circuit described in the aforementioned second patent document, the read-out operation is conducted through amplifying a potential difference between the node VMN when the charge read out from the memory cell is “0” data and the node VMN when the charge is “1” data. However, in order to amplify the potential difference by a sense amplifier, the amplification needs to be conducted after the negative potential has been converted to a positive potential. For this reason, with the circuit described in the aforementioned second patent document, after the negative potential is converted to a positive potential by using a voltage shift circuit [7], the read-out operation is conducted by a sense amplifier circuit [5]. However, the voltage shift circuit [7] described in the aforementioned second patent document has a large conversion loss, causing a problem in that the potential difference on the node VMN becomes smaller after the conversion. It is noted that numbers in the brackets above are reference numerals used in the document.